Abstract
Recently, progress has been made on the Intra Pattern Copy (IPC) tool for JPEG XS, an image compression standard designed for low-latency and low-complexity coding. IPC performs wavelet-domain intra compensation predictions to reduce spatial redundancy in screen content. A key module of IPC is the displacement vector (DV) search, which aims to solve the optimal prediction reference offset. However, the DV search process is computationally intensive, posing challenges for practical hardware deployment. In this paper, we propose an efficient pipelined FPGA architecture design for the DV search module to promote the practical deployment of IPC. Optimized memory organization, which leverages the IPC computational characteristics and data inherent reuse patterns, is further introduced to enhance the performance. Experimental results show that our proposed architecture achieves a throughput of 38.3 Mpixels/s with a power consumption of 277 mW, demonstrating its feasibility for practical hardware implementation in IPC and other predictive coding tools, and providing a promising foundation for ASIC deployment.
Abstract (translated)
最近，在JPEG XS的Intra Pattern Copy（IPC）工具方面取得了进展。JPEG XS是一种专为低延迟和低复杂度编码设计的图像压缩标准，而IPC通过执行小波域内的帧内补偿预测来减少屏幕内容中的空间冗余。IPC的一个关键模块是位移向量(DV)搜索，其目标是解决最优预测参考偏移问题。然而，DV搜索过程计算密集型高，给实际硬件部署带来了挑战。在本文中，我们提出了一种高效的流水线FPGA架构设计，用于优化DV搜索模块，以促进IPC的实际部署。通过利用IPC的计算特性以及数据内在重用模式进行了内存组织优化，进一步增强了性能。实验结果表明，所提出的架构实现了38.3 Mpixels/s的吞吐量和277 mW的功耗，在IPC及其他预测编码工具的实际硬件实现中证明了其可行性，并为ASIC部署提供了有前景的基础。
URL
https://arxiv.org/abs/2603.10671
